The fabrication processes for silicon chips often lead to the formation of small stress-induced silicon defects that may coalesce into dislocations or stacking faults that degrade the product functionality, yield and reliability. Examples of such processes include ion implantation, trench isolation and other dielectric isolation processes, trench capacitor processes, oxidation processes in general and film deposition processes. Results of stress-induced defects include gate and capacitor dielectric leakage, which may be yield or reliability defects.
Semiconductor silicon substrates, being crystalline are subject to shearing of one portion of the crystal with respect to another portion of the crystal along a specific crystal plane. Dislocations, which are postulated as crystalline defects, occur in different types including: edge dislocations, screw dislocations and declinations.
In dynamic random access memory (DRAM) technologies employing deep trench storage capacitors, the leakage requirements for the capacitor are very stringent, and monitor systems are introduced for the detection of process induced defects in the active area of the DRAM deep trench storage capacitors.
While methods exists for monitoring processes for defects and other methods exist for detecting stress during processes development, an efficient and sensitive monitoring systems for detecting stress-induced defects that could be used for both development and routine monitoring in manufacturing is limited. Therefore, a method is needed to detect the formation of silicon defects that is sensitive, simple, applicable to process monitoring and process development and applicable to logic and DRAM technologies.